This invention relates to amplifiers employing field effect transistors (FET). More particularly, it is concerned with metal-oxide-silicon (MOS) inverter amplifiers having DC biasing at the input.
Inverter amplifiers employing MOS FET's arranged in a series of inverter amplifier stages with capacitive coupling to their inputs are well-known. These circuits employ DC biasing at the input to each stage. It is desirable that the DC biasing voltage under quiescent conditions be approximately one-half of the supply voltage. With this biasing condition the amplifier can be operated at near maximum gain with maximum dynamic range and good linearity.
DC biasing of an MOS inverter amplifier can be obtained by connecting the input of an inverter stage to its output with a high impedance so that the input voltage is equal to the output voltage. Theoretically, with this arrangement the quiescent output voltage is in the middle of the transfer curve where the gain is near maximum, dynamic range is large, and linearity is good. However, if the gain of an inverter stage is to be large, the ratio of the dimensions of the two FET's of the stage are such that the transfer curve of the stage causes the quiescent output voltage to lie on the transfer curve at a point where the gain is not as high, the dynamic range is low, and the linearity is not as great. Furthermore, even with FET's designed so that theoretically the quiescent output voltage is in the middle of the transfer curve, variations in the parameters of the devices due to variations in processing and in ambient conditions cause the actual DC biasing point to shift away from the design point with consequent deterioration of the operating characteristics.